The IEEE P1596.3-1995 Draft 1.3 standard relates to the transmission of digital signals (bits) in a differential form using as a transmission medium two transmission lines adapted with 100 ohm impedance differentials. The transmission medium may be a pair of metal lines on a printed circuit board (PCB) of a personal computer, for example. The digital signals have a limited dynamic range, typically with a peak of 400 mV, for example. In general, the standard relates to high frequency signals up to 500 Mbit/s. The use of limited dynamic range signals minimizes the current consumption of the transmitter and allows for a high bit-rate.
The choice of differential signals reduces the noise generated in transmission. In fact, equal and opposite currents on two parallel tracks tend to minimize electromagnetic interferences (EMI). The differential signals also increase immunity to noise from other parts of the system, such as noise of a common mode type.
Compatibility with large common mode signals is required in the receiver defined by the above cited standard to ensure correct operation of the connection even in the presence of large noise levels on the local grounds of the transmitter and the receiver.
The receiver requirements are as follows:
(1) the input band is up to 500 MHz; (2) the minimum input amplitude has a 100 mV differential peak; (3) the common mode dynamic amplitude of the inputs is 0-2.4 V with a 3 V supply; and (4) the hysteresis is 25 mV at a minimum. Comparator structures satisfying one or more of these requirements are well known.
Requirements 1 and 2. Recently, high frequency and high sensitive comparator structures intended for Flash converters have been disclosed, for example. Such well known structures include several low gain amplification stages. However, they are synchronous structures, do not have hysteresis, and they are not "supply compatible".
Requirement 3. An input compatible common mode amplitude is dictated by the input circuit. There are several known circuits for operational amplifiers and comparators with a rail-to-rail compatible input. However, the hysteresis value tends to vary according to the input common mode unless gain compensation techniques for the input stage are used.
Requirement 4. Classic hysteresis comparators are well known and depicted in FIG. 2a and FIG. 2b with reference to the variables defined in FIG. 1. Both circuits are not appropriate for high frequencies. Moreover, in the case of the circuit of FIG. 2a, the value of the hysteresis depends on the voltage supply, while the circuit of FIG. 2b is not rail-to-rail compatible.